This application claims priority rights under 35 U.S.C. xc2xa7119 from French application No. 01/01335, filed on Jan. 31, 2001, the entire disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to the field of digital signal frequency dividers. The present invention more specifically relates to the forming of a fractional divider in a circuit from which several signals of same frequency shifted in phase with respect to one another can be extracted.
2. Discussion of the Related Art
The present invention is usable in phase-locked loops (PLL) which use a digital frequency divider in the regulation loop.
FIG. 1 very schematically shows in the form of blocks a conventional example of a phase-locked loop. Such a circuit is based on the use of a voltage-controlled oscillator (VCO) 1, the output of which provides a signal OUT representing the phase-regulated signal. As an input, the PLL receives a signal IN on which the output signal must be regulated. The signal IN is sent to a phase comparator 2 (xcex94"psgr") providing an error signal to a low-pass filter 3 (LPF), the output of which controls the VCO 1. A second input of comparator 2 receives a feedback signal corresponding to signal OUT having crossed a frequency divider 4. In the application of the present invention, divider 4 is a fractional divider.
Conventionally, to obtain a fractional divider, the frequency of the digital signal is divided by two different non-zero integers P and Q. The divisions by P and Q are alternately performed, as appropriate; an average division between these two values is thus obtained. The resulting signal thus actually corresponds to the input digital signal, the frequency of which is divided by a fractional number comprised between P and Q.
A disadvantage of conventional fractional dividers is that the resulting signal exhibits a phase error which is all the greater as values P and Q are distant from each other. Now, since P and Q are integers, the minimum interval between these two values is 1. Basically, the phase error or jitter of the resulting signal is proportional to the period of the input signal multiplied by the difference between values P and Q.
The present invention aims at overcoming the disadvantages of known fractional dividers in terms of phase error of the resulting signal. In other words, the present invention aims at improving the resolution of fractional dividers.
The present invention more specifically aims at providing a fractional frequency divider of a digital signal having a resolution step of 1/N, where N is a natural non-zero integer.
The present invention also aims at providing a programmable fractional divider.
To achieve these objects, the present invention provides a method of fractional division of a frequency of a digital signal based on N replicas of said digital signal shifted in phase with respect to one another by 2xcfx80/N. This method consists of selecting a first replica to generate the rising edge and a second replica to generate the falling edge, the first and second replicas of one period of the resulting signal being different from the first and second replicas used in the next period.
According to an embodiment of the present invention, the second replica of a current cycle forms the first replica of the next cycle.
According to an embodiment of the present invention, the replicas are chosen so that the edge of the second replica, which is useful in a current cycle, appears subsequently to the edge of same type of the first replica of the current cycle.
According to an embodiment of the present invention, to obtain a division ratio of (1+K/N), where K represents an integer, the sequence number AD2 of the second replica of a current cycle is obtained as a function of the sequence number AD1 of the first replica, by the following formula:
AD2=(AD1+K) modulo N.
The present invention also provides a fractional divider of a digital signal, including means for implementing the above-mentioned method.
According to an embodiment of the present invention, the fractional divider includes means for selecting, for each cycle of the resulting signal, a phase of a voltage-controlled oscillator providing the digital signal for one of the cycle edges and a different phase for the opposite edge.
According to an embodiment of the present invention, the resulting signal is provided by an output flip-flop having an output looped by an inverter on its input, a clock input of the output flip-flop being connected, through an inverter, to the output of a first multiplexer and a set input of the output flip-flop being connected to the output of a second multiplexer, the first and second multiplexers receiving the N phases of the signal to be divided.
According to an embodiment of the present invention, the multiplexer is controlled by a signal provided by an addressing flip-flop, said addressing flip-flops being assembled in series and a first addressing flip-flop receiving an address signal for selecting the phase of the current signal.
According to an embodiment of the present invention, the clock input of the first addressing flip-flop is connected to the output of the second multiplexer, the clock input of the second flip-flop being connected to the output of the inverter associated with the first multiplexer.
According to an embodiment of the present invention, the fractional divider includes a circuit for generating, for each cycle of the resulting signal, an address signal of selection of a phase of the digital signal based on an integral number of programming operations ranging between 0 and Nxe2x88x921.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.